Technical Field
The present disclosure generally relates to techniques for fabricating high performance fin field-effect transistors (FinFETs) and, in particular, to techniques for defect reduction in strained silicon transistors.
Description of the Related Art
Advanced integrated circuits often feature strained channel transistors, silicon-on-insulator (SOI) substrates, FinFET structures, or combinations thereof, in order to continue scaling transistor gate lengths below 20 nm. Such technologies allow the channel length of the transistor to be made smaller while minimizing detrimental consequences such as current leakage and other short channel effects.
A FinFET is an electronic switching device that features a conduction channel in the form of a semiconducting fin that extends outward from the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance in the “on” state and less current leakage in the “off” state than is possible in a conventional planar device. FinFETs are described in further detail in U.S. Pat. No. 8,759,874, and U.S. Patent Application Publication US2014/0175554.
Strained silicon transistors have been developed to increase mobility of charge carriers, i.e., electrons or holes, passing through a semiconductor lattice. Incorporating strain into the channel of a semiconductor device stretches the crystal lattice, thereby increasing charge carrier mobility in the channel so that the device becomes a more responsive switch. Introducing a compressive strain into a pFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in voltage applied to the transistor gate. Likewise, introducing a tensile strain into an nFET tends to increase electron mobility in the channel, also resulting in a faster switching response.
There are many ways to introduce tensile or compressive strain into transistors, for both planar devices and FinFETs. In general, such techniques typically entail incorporating into the device epitaxial layers of one or more materials having crystal lattice dimensions or geometries that differ slightly from those of the silicon substrate. Strain and mobility effects within an epitaxially grown crystal are tuned by controlling the elemental composition of the crystal. Such epitaxial layers can be incorporated into source and drain regions, into the transistor gate that is used to modulate current flow in the channel, or into the channel itself, which is a portion of the fin. For example, one way to introduce strain is to replace bulk silicon from the source and drain regions, or from the channel, with silicon compounds such as silicon germanium (SiGe). Because Si—Ge bonds are longer than Si—Si bonds, there is more open space in a SiGe lattice. The presence of germanium atoms having longer bonds stretches the lattice, causing internal strain. Electrons can move more freely through a lattice that contains elongated Si—Ge and Ge—Ge bonds, than through a lattice that contains shorter Si—Si bonds. Replacing silicon atoms with SiGe atoms can be accomplished during a controlled process of epitaxial crystal growth, in which a new SiGe crystal layer is grown from the surface of a bulk silicon crystal, while maintaining the same crystal structure of the underlying bulk silicon crystal. It has been determined that epitaxial SiGe films containing a high concentration of germanium, e.g., in the range of 25%-40%, provide enhanced electron mobility compared with lower concentration SiGe films. Thus, from the point of view of device performance, it is generally advantageous to increase the percent concentration of germanium atoms in the fins in a FinFET.
Alternatively, strain can be induced in the fin from below the device by using various types of silicon-on-insulator (SOI) substrates. An SOI substrate features a buried insulator, typically a buried oxide layer (BOX) underneath the active area. SOI FinFET devices have been disclosed in patent applications assigned to the present assignee, for example, U.S. patent application Ser. No. 14/231,466, entitled “SOT FinFET Transistor with Strained Channel,” U.S. patent application Ser. No. 14/588,116, entitled “Silicon Germanium-on-insulator FinFET,” and U.S. patent application Ser. No. 14/588,221, entitled “Defect-Free Strain-Relaxed Buffer Layer.”
While a strained silicon lattice is beneficial, creating strain by incorporating germanium atoms using existing methods tends to damage the crystal lattice. As a result, the lattice structures of germanium-rich films tend to be mechanically unstable, especially if they contain a high number of structural defects such as faults, or dislocations. Furthermore, a mechanically unstable SiGe fin may be structurally limited with regard to its aspect ratio, or height-to-width ratio. Such a limitation is undesirable because one advantage of a FinFET is that the fin, being a vertical structure, has a small footprint.